A capacitor is a fundamental two-terminal electronic device that may be manufactured in an integrated circuit. However, in an integrated circuit, it is often difficult to realize a well controlled capacitance value. The variation that results from the processes involved in the fabrication of integrated circuits may cause the value of a given capacitor to change by as much as 30% from device to device. Hence, several smaller capacitors are most often used by connecting them in parallel to create one large capacitor. The accuracy of the combined capacitance of these smaller capacitors can be better than 0.1%. Therefore, an array of capacitors is commonly used in integrated circuits. A capacitor array contains a plurality of individual capacitors positioned in rows and columns to allow for the routing of signals within the integrated circuit. One type of capacitor used in an integrated circuit is a “poly-poly” capacitor, which uses a parallel-plate structure that includes two polysilicon layers.
FIG. 1 illustrates a side view of the semiconductor layers forming a standard poly-poly capacitor in an integrated circuit. The capacitor 100 is formed by the polysilicon layers 106 and 108 where an oxide (detail omitted for clarity) between the polysilicon layers is thinner than normal inter-layer oxides. Beneath the capacitor 100 is a well 104 that is diffused into the silicon substrate 102. The well 104 is normally connected to a low impedance, low noise point in the circuit to help shield the capacitor from substrate noise. The polysilicon layers 106 and 108 are connected to a metal routing layer (metal 1) that is used to connect the capacitor 100 to other circuit elements or bond pads within the integrated circuit. Contact 114 connects the bottom polysilicon layer 106 to a first metal 1 routing track 110, and contact 116 connects the top polysilicon layer 108 to a second metal 1 routing track 112.
FIG. 2 illustrates a top view of the semiconductor layers forming a standard poly-poly capacitor in an integrated circuit. As shown and described above in connection with FIG. 1, the first metal 1 routing track 110 is connected to the bottom polysilicon layer 106 by way of contact 114. The second metal 1 routing track 112 is connected to the top polysilicon layer 108 by way of contact 116. Beneath the capacitor 100 formed by polysilicon layers 106 and 108 is the well 104 that is diffused into the silicon substrate 102.